1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly to such a method using local oxidation to thereby physically and electrically isolate regions from each other in which a device is to be fabricated.
2. Description of the Related Art
Several proposals have been made in order to prevent dimensional shift and decrease stress for a semiconductor fabricating process in which local oxidation is to be used for physical separation of regions in which a device is to be fabricated. Hereinbelow will be explained some of such proposals as prior art.
Japanese Unexamined Patent Public Disclosure No. 2-119137 has suggested a method for fabricating a MOS transistor. In this method, as illustrated in FIG. 1A, on a silicon substrate 301 is deposited a silicon oxide layer 302, then a silicon nitride layer 303 on the silicon oxide layer 302, and further a photoresist mask 304 on the silicon nitride layer 303. Then, the silicon nitride layer 303 together with the silicon oxide layer 302 are selectively removed by means of anisotropic etching, and at the same time are formed channels 305. Then, ion-implantation is carried out to the channels 305 to thereby form channel stopper layers 306.
Then, as illustrated in FIG. 1B, oxidation is selectively carried out with the silicon nitride layer 303 serving as a mask to thereby form oxide layers 307 in the channels 305, which physically and electrically isolates regions 320 from each other in which a device is to be fabricated. Then, both the silicon oxide layer 302 and the silicon nitride layer 303 are removed. Finally, the oxide layers 307 and the exposed silicon substrate 301 are covered with a gate oxide layer 308, which is in turn covered with a gate interconnection 309. Thus, a MOS transistor is completed.
Japanese Unexamined Patent Public Disclosure No. 63-217640 has also suggested a semiconductor fabricating method. In this method, as illustrated in FIG. 2A, on a silicon substrate 401 are successively deposited a silicon oxide layer 402, a polysilicon layer 403 and a silicon nitride layer 404 in this order. Then, the silicon nitride layer 404, the polysilicon layer 403 and the silicon oxide layer 402 are selectively removed by etching, thereby these layers 404, 403 and 402 do not exist in regions 410 which physically and electrically isolate regions 411 from each other in which a device is to be fabricated. Then, the exposed silicon substrate 401 is oxidized to thereby thin silicon oxide layers 405 within the regions 410.
Then, a silicon nitride layer 406 is deposited over the thin silicon oxide layers 405 within the regions 410. Then, as illustrated in FIG. 2B, the silicon nitride layer 406 is etched so that the silicon nitride layer 406 remains only along sidewalls of the deposited layers 402, 403 and 404. As a result, the polysilicon layer 403 is entirely covered with the silicon nitride layers 404 and 406. Then, regions in which no polysilicon layer exists are oxidized with the polysilicon layer 403 covered with the silicon nitride layers 404 and 406 serving as a mask, as illustrated in FIG. 2C. Thus, as illustrated in FIG. 2D, there are formed oxide layers 407 serving as regions which physically and electrically isolate active regions 408 in which a device is to be fabricated.
Japanese Unexamined Patent Public Disclosure No. 4-58532 has suggested another method of fabricating a semiconductor device. In this method, as illustrated in FIG. 3A, on a silicon substrate 501 are successively deposited a silicon oxide layer 502, a silicon nitride layer 503 and a silicon oxide layer 504 in this order. Then, the silicon nitride layer 503 and the silicon oxide layer 504 are etched only in regions 520 which will physically and electrically isolate regions 521 from each other in which a device is to be fabricated, so that a reduced thickness of the silicon oxide layer 502 remains. Then, the thus residual silicon oxide layer 502 is etched by means of wet etching, by which is also formed spaces 507 having a length of approximately 100 angstroms, beneath the silicon nitride layer 503. Then, a resultant is entirely covered with a silicon nitride layer 505 for use of off-set formation, which is further entirely covered with a silicon oxide layer or an HTO layer 506, as illustrated in FIG. 3A.
Then, as illustrated in FIG. 3B, the HTO layer 506 and the silicon nitride layer 505 are back-etched to thereby form sidewalls 508 along the deposited layers 502, 503 and 504. Then, ion is implanted to the exposed silicon substrate 501 to thereby form impurity layers 509. Then, the sidewalls 508 composed of the silicon oxide layer 506, and the silicon oxide layer 504 are removed, as illustrated in FIG. 3C, and then there are formed oxide layers 510 which physically and electrically isolate the regions 521 from each other in which a device is to be fabricated, as illustrated in FIG. 3C. Finally, as illustrated in FIG. 3D, the silicon nitride layer 505, the silicon nitride layer 503 and the silicon oxide layer 502 are removed.
The first mentioned prior art has just a one step more than than LOCOS separation, specifically, a step of etching a silicon substrate. However, the selective oxidation causes dimensional shift because sidewalls 301a of the silicon substrate 301 in the channels 305 are also oxidized. In addition, the oxide layers 307 for isolating the regions 320 from each other are formed to be a barrel in shape, and thereby electric field is concentrated to ends 310 of the channels 305 with the result that a threshold voltage of a fine transistor is lowered. Thus, the firstly mentioned prior art has a problem like this which is so-called reverse narrow channel effect.
In the second mentioned prior art, a stress can be relaxed to some degree by forming the silicon oxide layer 405 beneath the silicon nitride layer 406, however, the number of steps is increased because there are additionally required the steps of forming the silicon oxide layer 405, forming the silicon nitride layer 406 and carrying out etching back. In addition, though the silicon oxide layer 405 can relax a stress to some degree when the oxide layers 407 are formed, the relaxation of stress is not sufficient because the dimensional shift is suppressed by the silicon nitride layer 406. Furthermore, similar to the first mentioned prior art, the second mentioned prior art has also a problem of the reverse narrow channel effect because the oxide layers 407 are formed to be a barrel in shape.
The third mentioned prior art makes it possible to relax a stress to some degree by forming the spaces 507. However, the method is required to have additional steps such as steps of etching in order to form the spaces 507, forming the silicon nitride layers 505 and the silicon oxide layers 506, and etching-back the layers. In addition, this method has smaller ability of physical separation of regions in which a device is to be fabricated than the other methods because the silicon substrate 501 is not etched. Furthermore, when a surface step of the silicon substrate 501 is intended to be made smaller after the formation of the oxide layers 510, ends 510a of the field oxide layers 510 are sunk below the surface of the silicon substrate 501, as illustrated in FIG. 3D. Similar to the first and second mentioned prior arts, the third mentioned prior art has also a problem of the reverse narrow channel effect.
Thus, the conventional art cannot simultaneously solve the problems of the relaxation of a stress, the dimensional shift, the increase of the number of fabrication steps, and the reverse narrow channel effect.